Digital Heart Rate Variability Monitoring System

In this paper we describe the implementation of an application specific integrated chip (ASIC) for digital heart rate variability monitoring system. The proposed system extracts the R peaks from the input ECG signals using peak detection algorithm and stores the computed R-R intervals into an efficient SRAM as the internal memory. A histogram sorter sorts the R-R intervals which are then indexed into histograms representing the variation in patient’s heart rate over a period of time. The system has been designed and synthesized for a 0.5 μm CMOS technology and placed in TCU-4 chip with area of 3x3 mm including core and pad rings. Additional multiplexer and de-multiplexer units were incorporated in the design to allow for testing of the memory function. They were then fabricated by MOSIS and returned in packaged form. The parts received from MOSIS were tested using LV 512 tester at 2.5 MHz, where 4 out of the 5 parts received passed the testing.